A memory patent can look simple on paper. Identify the claimed structure, find the matching feature in the accused product, and show that every claim limitation is present. DRAM and HBM cases rarely work that way, because the limitation that decides the case often sits inside the silicon, where no datasheet reaches.
Finding a datasheet that says a product is DDR5 or HBM3 is easy. JEDEC, the Solid State Technology Association that writes most memory standards, publishes the specifications those labels refer to, and a DDR5 specification describes itself as the minimum set of requirements a compliant device must meet. The internal design above that minimum belongs to the manufacturer. A patent owner whose claim covers cell layout, peripheral circuitry or die stacking therefore has to prove the implementation directly. That usually means opening the part and imaging it with SEM and TEM, then adding circuit extraction and electrical testing where the claim needs them, and then tie each finding to the claim language through an expert who can defend the method.
This article covers where that gap opens in memory patent litigation: which claim types need physical evidence, why the accused sample has to be pinned down before any lab work, what SEM and TEM images can and cannot establish, why HBM stacks are harder than a single die, and how teardown findings become claim chart evidence that keeps observation separate from opinion.
Key Takeaways
- A JEDEC standard such as DDR5 sets the minimum requirements a compliant part must meet. It does not show how a given manufacturer built the cells, circuits or stack inside.
- Interface and signaling claims can often be charted from standards, datasheets and electrical tests. Cell, array, peripheral-circuit and stacking claims usually need teardown evidence.
- The accused part has to be identified and tied to the physical sample before any destructive work starts, because memory lines ship in several revisions and die configurations.
- HBM adds a stack problem: the evidence has to show which die holds the claimed feature and how it connects to the dies above and below it.
- A usable claim chart keeps three statements apart: what the SEM or TEM image shows, what an engineer interprets it to be, and the expert’s opinion on the claim limitation.
Why Standards Compliance Doesn’t Prove Infringement
Memory products are hard infringement targets because the claim limitations that decide the case can sit below anything the product shows publicly.
A product page may give a DRAM density, data rate, organization, voltage, package type or HBM generation. The JEDEC standard defines the expected interface and protocol. Neither tells you how the manufacturer arranged its memory cells, sense amplifiers (the circuits that read the small charge stored in each cell), peripheral circuits, power-management structures or internal interconnects.
What a DDR5 SDRAM Standard Actually Defines
DDR5 is the fifth generation of double data rate SDRAM, synchronous DRAM whose operations are timed to a clock signal. JEDEC published the JESD79-5 DDR5 SDRAM standard in July 2020 and its latest revision, JESD79-5D, in November 2025. The standard covers features, functions, AC and DC electrical characteristics, packages and ball and signal assignments, and states that its purpose is to set the minimum requirements for compliant 8 Gb to 32 Gb devices.
That scope makes a standard useful evidence for interface claims. A DDR5 datasheet, or the spec sheet for a DDR5 RAM module, can show that a part supports a timing mode, a command or a burst length. It cannot show the physical arrangement of the circuit blocks that deliver those features. Take a claim that requires a particular relationship between a memory array and its peripheral circuitry. A datasheet can establish that the device has a memory array. It normally cannot establish where the peripheral blocks sit or how they connect to the array.
HBM follows the same pattern. Under the HBM3 standard each stack supports up to 16 channels, and the vendor decides how those channels are spread across the DRAM dies in the stack. JEDEC’s HBM4 standard, published in April 2025, also leaves some supply voltage levels to the vendor. A specification can confirm that a product conforms to an HBM generation while saying nothing about through-silicon via geometry, die construction or the circuitry on the base die. Lumenci’s JEDEC memory standards whitepaper covers how the standards are organized. When the standard itself is the basis of an assertion, the analysis moves into standard essential patents, a separate question from proving what is inside the silicon.
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The Netlist v. Micron Verdict
Memory disputes carry large sums. In Netlist, Inc. v. Micron Technology, Inc., No. 2:22-cv-00294 in the Eastern District of Texas, a jury found on May 23, 2024 that Micron willfully infringed U.S. Patent Nos. 7,619,912 and 11,093,417 and awarded $425 million on the ’912 patent and $20 million on the ’417 patent, $445 million in total. The accused products were Micron DDR4 RDIMMs and LRDIMMs, registered and load-reduced memory modules used in servers. The court denied Micron’s post-trial motions and upheld the award in 2025.
Validity was fought on a separate track. The Patent Trial and Appeal Board (PTAB), the USPTO body that decides inter partes review (IPR) challenges, found claim 16 of the ’912 patent unpatentable in April 2024, about a month before trial, and Netlist appealed. An infringement win in a memory case can still be exposed at the patent office, so the proof has to hold up alongside a validity fight.
What Gets Claimed in Memory Patents
Memory claims can target several different technical layers, and each layer calls for different evidence.
Interface limitations can often be proven from public documents and testing, while internal structural limitations usually need physical evidence from the accused part. A standard can be strong evidence that a product was designed to meet an interface requirement, but it does not prove that every internal implementation described in a patent exists inside that product.
How DRAM Infringement Gets Proven
The lab sequence for any chip teardown, from decapsulation through delayering, imaging, netlist extraction and documentation, is covered step by step in Semiconductor Reverse Engineering: The Complete Process Explained. The points below are the ones specific to memory claims.
Tie the Accused Product to the Physical Sample
A defensible DRAM investigation starts by identifying exactly which product is accused. Memory products ship in multiple revisions, process generations, densities and die configurations. A teardown of the wrong part can produce accurate findings about a chip that is not the accused product, and those findings cannot prove the claim limitations for the part that is. Infringement analysis has to connect the evidence to the specific accused product and to the claim limitations as the court construes them.
Product pages, datasheets, regulatory filings, packaging and marking information help establish product identity. The investigation then needs a documented chain from the commercial product to the sample on the bench.
Plan Decapsulation and Delayering Around the Claim
Decapsulation removes the package to expose the die. Delayering then removes the chip’s metal and insulating layers one at a time so each can be imaged. Both steps destroy material, so the plan has to start from the asserted claim. Before anything is removed, the team should know whether it needs to show where arrays sit, how they divide into regions, where peripheral circuitry sits relative to the arrays, how signal lines are routed, or whether a claimed structure repeats across the die.
Laser-based methods are widening what a lab can expose. A 2026 Scientific Reports study described a single femtosecond-laser workflow that decapsulated a package-on-package device, removed its DRAM, exposed its redistribution layers and cross-sectioned the logic die, with SEM used to check the results. Earlier work from the same research group used a green femtosecond laser to remove chip layers more evenly, checked with confocal microscopy and SEM.
SEM and TEM Evidence in Memory Patent Cases
Once a layer or cross-section is exposed, most of the physical proof in a memory case comes from two electron microscopes. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) answer different questions, and memory cases often use both.
SEM is the workhorse for layout questions: where arrays sit, how interconnects route, how contacts and vias line up across layers. TEM is the tool for claims that turn on what a single cell or transistor is made of, such as the films in a capacitor stack. In HBM, SEM cross-sections through the stack can show TSVs and bonding layers between dies. Materials analysis such as EDS or EELS, run alongside the microscope, can identify what a layer is made of when a claim names a material.
What an Image Has to Show
For litigation, each image has to answer a question the claim raises. If a claim requires a particular arrangement of conductors, the image should identify those conductors and show how they relate. If it requires a structure within a memory cell, the analysis must locate that structure and explain how it corresponds to the limitation. Whether the structure satisfies the claim is a legal question, separate from the technical fact that the structure can be seen.
The record behind each image carries as much weight as the image. It should show which sample and region were imaged, how the layer or slice was prepared, the instrument settings, and how the imaged area relates to the rest of the die. Without that record, an opposing expert can argue the image shows a different region, an artifact of preparation, or a different part.
When SEM and TEM Need Circuit Extraction and Electrical Testing
Imaging shows which structures are present and where they sit. Circuit extraction reconstructs how those structures are wired together and how they operate, working from repeated layout patterns, interconnects, transistor-level features and known design relationships. A claim to a specific sense-amplifier arrangement needs this step. Showing that the product has sense amplifiers does not meet that limitation. The investigation has to establish the claimed configuration and its electrical relationship to the surrounding memory circuitry.
Electrical testing covers limitations that are easier to show through behavior: timing, voltage, current draw, signal relationships or responses to set operating conditions. Behavior has a limit as evidence, since a device can produce the same external behavior through different internal designs. A product shown to perform function X has not yet been shown to contain the claimed circuit that performs X. The strongest investigations combine physical and electrical evidence.
Why HBM Is Harder to Prove
An HBM package holds more than one memory die. HBM3 parts stack 8 to 12 DRAM dies connected by through-silicon vias (TSVs), vertical connections that run through each die, and the DRAM dies sit on an interface base die. The investigation now has to answer questions a single-die DRAM case does not raise.
- Which die contains the claimed feature?
- Is the feature repeated on every memory die, or present on one layer only?
- Does the claim cover a relationship between two dies, or a connection that passes through the stack?
- Is the relevant circuitry on a DRAM die, the base die, or both?
Sample preparation decides whether those questions can be answered. Cross-sectioning a stack can destroy the evidence the team is trying to keep. Removing layers can expose a target region while erasing its relationship to the layers above and below it. The stack’s own structures, such as TSVs, bonding layers and the base die, can also be claim limitations in their own right.
For an HBM claim the evidence is usually a sequence: package, stack, individual die, cross-section, TSV or bonding structure, circuit region, electrical behavior. Each step has to be documented so the relationship between layers survives the teardown.
Turning Teardown Findings Into Claim Chart Evidence
Sharp photographs alone do not make a teardown into a claim chart. The mapping usually runs from claim limitation to accused-product feature, evidence source, technical interpretation and expert conclusion.
Suppose a claim requires a particular circuit relationship inside a DRAM die. The evidence package might hold the sample identification record, photographs of the package and die, a delayering record showing how the relevant layer was exposed, SEM images of the region, extracted circuit diagrams or reconstructed layouts, electrical test results where relevant, a comparison against the patent’s figures and claim language, and an expert explanation tying it together.
Claim charts give that material a structure for checking whether every limitation has evidence behind it. The chart should also keep three kinds of statement apart:
- “SEM image shows three parallel conductive structures” is an observation.
- “These structures correspond to the claimed bit lines” is a technical interpretation.
- “The accused product therefore satisfies limitation 1(c)” is an expert infringement opinion.
Keeping them apart pays off when expert testimony is challenged. The expert must explain how the structure was identified, how the analysis was done and why the evidence supports the claimed correspondence. Federal Rule of Evidence 702, as amended in December 2023, requires the party offering the expert to show that it is more likely than not that the opinion reflects a reliable application of the expert’s methods to the facts. Findings that are documented, reproducible and tied to specific claim limitations meet that standard far more easily. Semiconductor expert testimony has to cover both what an image shows and why the method behind it is reliable.
A chain like this one tends not to survive scrutiny: the product is DDR5, DDR5 uses feature X, so this die must use feature X, so the patent is infringed. It is a reasonable starting hypothesis for an investigation. The chain that holds up runs from an identified commercial sample, to a physically examined die, to an observed structure that was reconstructed or tested, mapped to the claim limitation, and explained by an expert.
How Lumenci Builds Memory Infringement Evidence From Package to Claim Chart
Lumenci plans memory investigations from the asserted claims, so the lab work, the imaging and the expert opinion all trace back to specific limitations.
- Claim-first lab planning. Lumenci engineers sort each asserted limitation by the evidence it needs, interface, structural or behavioral, before a sample is opened, and sequence destructive steps to preserve what the claim requires. Reverse engineering services
- In-house delayering and imaging. Lumenci’s delayering lab processes individual metal and polysilicon layers using etching, polishing and cross-sectional imaging to build circuit schematics and interconnect maps, with SEM, TEM and EDS/EELS materials analysis.
- Memory and stacking experts who testify. Lumenci’s semiconductor expert witnesses cover DRAM, SRAM and NAND, JEDEC DDR, LPDDR and HBM standards, hybrid bonding and 2.5D/3D packaging, so the expert who explains the teardown can also defend its method at deposition and trial.
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- Charts that separate observation from opinion. Findings flow into claim charts that label what was observed, what was inferred and what the expert concludes.
- Track record. Lumenci experts mapped structures across 14 devices and 20 patents in an OLED reverse engineering engagement, and the firm has served 200+ clients, analysed 100,000+ patents and supported $3.5B+ in verdicts, settlements and cost savings.
Talk to Lumenci’s semiconductor team about a memory matter.
Conclusion
Memory patent litigation turns on evidence the product literature does not carry, and most of that evidence comes out of SEM and TEM work on the accused part. HBM’s growing use in AI and high-performance computing servers means more claim limitations will concern structures inside dense stacks. Start from the claim: sort limitations into those a standard, datasheet or electrical test can show and those hidden behind the package, then plan the teardown around the second group before the sample is opened.
Before any lab work begins, iLumOS, Lumenci’s expert-powered patent intelligence platform, can help teams narrow which memory patents and products are worth investigating, with Lumenci experts validating each lead.
Table of Contents
Frequently Asked Questions
What is SDRAM?
SDRAM (synchronous dynamic random-access memory) is DRAM whose operations are timed to a clock signal. DDR5 is the fifth generation of double data rate SDRAM, defined by JEDEC standard JESD79-5.
Does JEDEC compliance prove a memory product infringes a patent?
Only for limitations the standard actually defines. Compliance shows that a product meets the standard’s interface requirements. Claims to cell layout, circuitry or stacking still need physical or electrical evidence from the accused part.
Can a DDR5 RAM datasheet be used as infringement evidence?
Yes, for interface, signaling and timing limitations, often backed by protocol traces or electrical tests. A datasheet rarely shows internal structure, so structural limitations need teardown evidence.
What is the difference between SEM and TEM in a chip teardown?
SEM scans the surface of an exposed layer or cross-section and is the main tool for imaging interconnects, contacts and vias. TEM sends electrons through an ultra-thin slice and resolves finer detail, such as thin films and transistor gates.
Why is HBM3 harder to analyze than a single DRAM chip?
An HBM3 stack holds 8 to 12 DRAM dies joined by TSVs above a base die. The evidence has to show which die holds the claimed feature and how it connects through the stack, and cutting into the stack can destroy those relationships.
What happened in Netlist v. Micron?
In May 2024 an Eastern District of Texas jury found that Micron willfully infringed two Netlist memory-module patents and awarded $445 million. The PTAB had found the key ’912 patent claim unpatentable a month earlier, and Netlist appealed that decision.
Who explains memory teardown evidence at trial?
A testifying technical expert, usually a semiconductor or memory design specialist. Under FRE 702 the expert must explain how each structure was found and show the method was reliably applied.
